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SHA-1: A Secured Hash Algorithm

• Description

This core is the fully compliant implementation of the NIST FIPS PUB 180-2 Secure Hash Algorithm - 1.

It produces output of 160 bit message digest for the input messages of up to (264 - 1) bits. The input must be in multiple of 8 bits.

• Features of Implemented Core
• Automatic message length calculation and padding
• On chip Block RAM used
• For last 512 block - requires 66 clock cycles
• For other 512 block - requires 68 clock cycles
• Core available in synthesizable VHDL
• Core Facts

Device Family	Virtex E (xcv1600e - 8fg1156)
Slices	1098
IOB	134
CLKIOB	1
System Clock	28.571 MHz
Block RAM	1
Throughput	445.14 Mbit/s