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MD5: Message Digest Algorithm

• Description

This core is the fully compliant implementation of the MD5 Message-Digest Algorithm, as described in rfc1321. It produces an output of 128 bit message digest (hash value) for the input messages of arbitrary length.

The MD5 core processes an input in successive 512 bit blocks. It produces a 128 bit message digest. The input must be a serial input and could be of arbitrary number of bits.

• Features of Implemented Core
• Automatic message length calculation and padding
• On chip Block RAM used
• Clock cycles required for the last message block

S.No.	Data Length in message block	Clock Cycles required for calculating intermediate value	Additional clock cycles required for calculating final hash value
1.	Less than 448	Not Applicable	73 + (14 - total number of completely filled 32 bit words
2.	448 < data length < 480	70	87
3.	480 < data length < 512	69	87
4.	Equal to 512	67	89

• Clock Cycles for other message blocks

S.No.	Data Length in message block	Clock Cycles required for calculating intermediate value	Additional clock cycles required for calculating final hash value
1.	512	67	Not Applicable

Core available in synthesizable VHDL
• Core Facts

Device Family	Virtex E (xcv1600e - 8fg1156)
Slices	1098
IOB	134
CLKIOB	1
System Clock	28.571 MHz
Block RAM	1

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