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3DES: Triple Data Encryption Standard, an important symmetric block cipher

• Description

The core is the fully compliant implementation of the Triple DES encryption Algorithm. The TDes core accepts a 64 bit plaintext input word (Data_in) and generates 64 bit ciphertext word using a supplied 56 bit keys (K1, K2 and K3). Encryption or Decryption is selected by En_De signal. After 48th clock cycle, status indicates that the output is ready. The standard specifies the following keying options for the keys (K1, K2, K3). - Keying Option 1: K1, K2, and K3 are independent keys; - Keying Option 2: K1 and K2 are independent keys and K3 = K1; - Keying Option 3: K1 = K2 = K3 - In the last case, the triple DES algorithm coincides with the DES algorithm, providing backward compatibility

• Features of Implemented Core
• Both encryption and decryption are supported
• Encryption and Decryption is performed in 48 clock cycles
• No dead cycles for key loading and mode changing
• Core available in synthesizable VHDL
• Core Facts

Device Family	Virtex E (xcv400e - 8bg432)
Slices	512
IOB	300
CLKIOB	1
System Clock	76.775 MHz
Throughput	307.1 Mbit/s