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Home Our Services Programming Tools Business Unit Compilers Development of 'DSP C' compiler 16-bit fixed point DSP

Development of 'DSP C' compiler 16-bit fixed point DSP

• Requirements
One of our Japanese customers required a compiler for a 16-bit DSP processor for their in-house application development. The CCDSP compiler should support DSP C language. The main requirement of the compiler is that the compiler


• Should support DSP C specification.
• Should be maintainable
• Should have low defect rate.
• Challenges
• Building over the legacy code
• Optimizing to effective utilize DSP processor's architecture


• Solution
• Environment

OS	Windows
Language/Platform	C
Development model	Incremental development model.
Quality validation tools	Numega Dev Partner Studio to determine the test coverage and check for memory errors/ leaks QAC for static analysis of code

• Description

The requirements provided by the customer were brief. The team analyzed the customer's requirement and prepared detailed specification and got the customer's approval. After the customer's approval, a detailed Project Plan was prepared. The compiler was built using Incremental Development Model. The project had 6 increments.

The team was built from scratch. Initially, the team comprised of only 2 members. The two members were quite naive with respect to DSP and compilers. They studied about DSP and compiler concepts, and prepared the functional Specification. Later, 5 new members joined the team. Training was provided to the new members to understand the DSP and compiler concepts. Later, 6 more members joined the team. During the peak development period, the team had 13 members.

To build a DSP compiler, the first pre-requisite was to understand the basics of DSP, the DSP applications, and see the compiler from user's point of view. To understand the DSP assembly, the team performed hand-coding of FFT, which is a DSP application. This exercise helped in learning the following:

• Allocating registers effectively and optimal utilization of resources
• Combining multiply and addition operations into a single MAC operation
• Achieving effective Memory Organization
• Bit-reverse Addressing
• Modulo Addressing
• Increasing scope of parallelism (ILP)
• Loop Unrolling
• Zero Overhead Loop

The DSP compiler was built over the front-end of a RISC compiler. The RISC compiler was already built for the same customer. It was decided by the customer to use the front-end of the RISC compiler as front-end of the DSP compiler. This was a challenging task since it required modification in legacy code. The team listed the features of the RISC front-end and analyzed if these features were applicable to DSP compiler. Features that were not applicable to our DSP compiler were blocked.

Since the development was done over the front-end of a RISC compiler, the team had to understand the existing design of the front-end of a RISC compiler. This was achieved by writing test programs. These test programs were then debugged and the existing design was understood. Team members worked on individually features and came out with a design that would not disturb the existing system.

Reviews and discussions were made by the team members to finalize the design. All team members were responsible for approving the final design. The design was documented in the source code as file and function headers. During development, reviews of the project artifacts were carried out on a daily basis. It was ensured that all the project artifacts were reviewed. Coding standards were followed strictly and the code was documented such that code can be reviewed, unit tested and maintained easily. The design was documented on source itself in format as required by a tool called "doxygen" which generated documentation from source. This ensured that code and documentation always remained in sync. Static analysis of the code and checking memory error / resources leaks were done on a regular basis using quality validation tools.

The final product was delivered on time and there were no last minute surprises or showstoppers. The main reason for this was our incremental approach. Every increment delivery was treated as if it is a final delivery and was delivered on time. The DSP compiler is presently in its maintenance phase.

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