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Home -> Our Services -> Programming Tools BU -> Debugger / Simulator -> Upgrading an existing simulator debugger to support additional targets

Upgrading an existing simulator debugger to support additional targets

Requirements

One of our Japanese customers required upgrading their 3 of their existing simulator to support additional target processors. The additional targets to be supported and the target that was already supported by the simulator used the same processor core. So the base simulation functionality was common. The targets to be supported by the simulators differed in the following aspects:

  1. Support for FPU instructions
  2. Support for DSP instructions
  3. Pipelining
  4. Memory organization
  5. Cache organization
  6. Exception handling

Challenges

  • Understanding existing implementation
  • Understanding advanced processor architectures
  • Defect prevention / not introducing defects

Solution

  • Environment
    OS
    Windows
    Language/Platform C
    Development model Incremental development model
    Quality validation tools
    • Numega Dev Partner Studio to check for memory errors, memory leaks and test coverage
    • QAC for static analysis of code
  • Description

    The first difficult phase in a maintenance or upgrade work is to understand the existing implementation and its interfaces. In a maintenance or upgrade work the ability to test the product to start with is also important. So our first task was to write test cases and to use the tests to debug and single step through the code to understand it. Our understanding was documented on the source code itself.

    Then we split the work involved in supporting the additional target across different milestones. This allowed us to concentrate on specific features in each milestone. Before adding a new functionality we first developed tests for the new functionality. This allowed us to single step and debug the implementation while it is being developed.

    The functionalities to be supported or modified include complex specifications like multi-stage pipelining, cache organization and memory management unit. Understanding these required reasonable hardware knowledge and understanding of processor architectures. The relevant materials are read and the team discussed it frequently to validate the understanding of the team members.

    Once we completed adding all the functionalities to support the new target, we calculated the code coverage. Additional tests were added to cover those portions of the code which are not exercised by the test cases. We reached test coverage of close to 100%.