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Home -> Our Services -> Embedded Systems -> FPGA Solutions -> ADPCM

ADPCM

Description

G.726 is an ITU-T defined codec Standard for audio speech. This Standard defines the technique for performing compression and expansion of speech wave forms for transmission, storage and reconstruction.

The ADPCM encoder receives a PCM input bit flow at 64kBPS and processes it to produce a 40, 32, 24 or 16 KBPS output.

The ADPCM decoder receives an input bit flow at 40, 32, 24 or 16 KBPS and processes it to produce a 64KBPS output.

Features of Implemented Core
  • Supports Configurable bit rates 16, 24, 32, 40 KBPS
  • Supports A-Law and ยต-Law Configuration
  • 128 duplex channel encoding / decoding
  • On chip Block RAM used
  • 9 clock cycles to process a sample
  • ITU-T Compliant
  • Core available in synthesizable Verilog

Core Facts

Device Family Virtex E (xcv200e - 8bg352)
Slices 2279
IOB 48
CLKIOB 1
System Clock 20 Mhz
Throughput 18