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Home -> Our Services -> Embedded Systems -> FPGA Solutions -> DES: Data Encryption Standard

DES: Data Encryption Standard, an important symmetric block cipher

  • Description

    This core is the fully compliant implementation of the NIST FIPS PUB 46-3 Data Encryption Algorithm (DES).

    The DES core accepts a 64 bit plaintext input word (Data_in) and generates 64 bit ciphertext word using a supplied 56 bit key (Key). Standard DES as described required 16 rounds for a complete encryption.

  • Features of Implemented Core

    • Both encryption and decryption are supported.
    • Encryption and Decryption are performed in 16 clock cycles
    • Suitable for Electronic Codebook (ECB), Cipher Block
    • Chaining (CBC), CFB and OFB implementations
    • No dead cycles for key loading and mode changing
    • Core available in synthesizable VHDL
  • Core Facts

Device Virtex E (xcv200e - 8fg456)
Slices 306
IOB 188
CLKIOB 1
System Clock 100.321 MHz
Throughput 401.284 Mbit/s