DSA: Digital Signature Algorithm
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Description
This core is a fully compliant implementation of the Digital Signature Algorithm, as described in Federal Information Processing Standards Publication 186-2, dated 27 January 2000.
The DSA core accepts input words in terms of 32 bits. It then generates or verifies signature depending upon the value of input port sig_gen_ver.
The size of parameters used is - p is a prime modulus, where 2^L-1 < p < 2^L for 512 < L - q is a prime divisor of p - 1, where 2^159 < q < 2^160
- g has order (q mod p) - x is such that 0 < x < q - y is g ^ x mod p - k is such that 0 < k < q
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Features of Implemented Core
- Both signature generation and signature verification can be done by the same core.
- SHA-1 is the inbulit core
- Core available in synthesizable VHDL
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Core Facts
| Device |
Virtex E (xcv3200e - 8fg1156)
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| Slices |
21215 |
| IOB |
299 |
| CLKIOB |
1 |
| System Clock |
10.692 MHz |
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